1. Field of the Invention
The present invention relates to a phase locked loop (PLL) circuit and a clock reproduction circuit. More particularly, the invention relates to a PLL circuit generating a clock signal synchronized with an input signal in phase and a clock reproduction circuit using the same.
2. Description of the Related Art
In order to accurately reproduce a received data in a reception device in a communication system, it becomes necessary to extract a clock component synchronized with the received data. For extraction of the clock component and reproduction data, PLL circuits have been used widely.
In SONET (Synchronous Optical Network) system as one of communication systems, a CDR (Clock and Data Recovery) circuit using the PLL circuit has been employed in order to reproduce a clock and a data. In order to adapt to a jitter specification (standard) in the SONET system, a frequency of a VCO (Voltage-controlled oscillator) of the PLL circuit as a clock extraction circuit of the CDR circuit has to accurately match with a received data speed.
Now, consideration is given for the case where the CDR circuit is used in an optical transmission system of 10 Gbps band. While the most typical transmission speed of the SONET system is 9.95 Gbps, data speed from 10.6 Gbps to 10.8 Gbps is present in a WDM (Wavelength Division Multiplexing) optical transmission system having FEC (Forward Error Correction), and so forth depending upon FEC algorithm. For this reason, the PLL circuit for clock reproduction used in the CDR circuit is required to have a wide lock range from 9.9 Gbps not applied FEC to 10.8 Gbps applied FEC, namely the lock range corresponding to about 1 GHz. In order to realize the PLL circuit having such wide lock range, the VCO forming the PLL circuit is required to have a wide variable frequency range.
Here, even in the foregoing optical transmission system, down-sizing and reduction of power consumption of the optical transmitting and receiving device are required. For this purpose, an operation power source voltage tends to be lowered. As a result, an operation voltage of the PLL circuit also becomes low voltage in the extent of about 3V. In such low voltage, a dynamic range of the circuit naturally becomes small. Associating therewith, it is inherent to lower a control voltage of the VCO.
In this circumstance, in order to enable the VCO to realize the wide variable frequency range set forth above, the VCO having high gain (high sensitivity) becomes necessary. For example, in case of the optical transmitting and receiving device in the optical transmission system set forth above, the gain (sensitivity) of the VCO required has to have quite high gain as high as 1 GHz/V. However, when high gain as high as 1 GHz/V is provided as the gain for the VCO, it can quite sensitively follow to external or internal noise in steady operation state to cause increasing of jitter to make the system unstable. As a result, difficulty is encountered in satisfying jitter specification of the SONET system set forth above.
Namely, while it becomes necessary to set the gain of the VCO high for realizing wide variable frequency range in a limited control voltage range, sensitivity to a high range noise component from a phase comparator or a noise generated in an internal circuit which cannot be blocked by a loop filter in the PLL circuit, becomes high to increase jitter. As a result, obtaining wide lock range and improvement of jitter characteristics is a relationship of so-called trade-off. Therefore it has been demanded to achieve both of obtaining wide lock range and improvement of jitter characteristics.
Here, reference is made to U.S. Pat. No. 5,012,494, there has been disclosed a PLL circuit having two control loops using the VCO having two inputs (two control input terminals). FIG. 9 shows a block diagram of the PLL circuit disclosed in the above-identified U.S. Pat. No. 5,012,494. In FIG. 9, an input data and a clock signal by a VCO 12 are input to a digital type frequency phase comparator (FD/PD) 11 for detecting a phase difference. A phase difference detection output S11 is supplied to one of two inputs of the VCO 12, and in conjunction therewith, is an input of an integrator (INTEG) 13. An integrator output S12 is supplied to the other of two inputs of the VCO 12.
Namely, by the output S11 of the frequency phase comparator 11, fine adjustment (phase: offset factor) of the VCO is controlled, and by integrated output S12 resulting from integration of the output S11 by an integrator 13, rough adjustment (frequency: centering factor) of the VCO 12 is controlled to form a dual-loop structure.
The frequency phase comparator 11 of FIG. 9 has a digital circuit construction having a frequency difference detection characteristics of the input data and the reproduction clock by the VCO as digital characteristics shown in FIG. 10B. Namely, the detection output (PD output) becomes a binary data which becomes high level when a phase difference is in a range between 0 to π, and becomes low level when the phase difference falls in a range between −π to 0.
Here, referring to FIG. 10A, a characteristic chart shows the case of a phase comparator which has a phase comparison characteristics of analog characteristics. In a phase difference in a range of −π to π, the phase comparison characteristics becomes linear with a constant gradient to be the characteristics of the analog phase comparator. A gain of such analog phase comparator has a linear gradient as shown in FIG. 10A. The gradient is always constant irrespective of amplitude of the jitter of the input signal. However, in case of the digital phase comparator shown in FIG. 10B, since the gradient of the characteristics is infinite, the gain is theoretically infinite. However, in practice, a shown in one-dotted line, the characteristics of the digital phase comparator has finite gradient and the gradient is variable depending upon amplitude of jitter of the input signal.
Accordingly, the gain of the frequency phase comparator 11 in the conventional PLL circuit shown in FIG. 9 inherently fluctuates. As a result, an open loop gain of the circuit shown in FIG. 9 inherently fluctuates. This means that the transmission characteristics of the closed loop of the PLL circuit can fluctuate to make the PLL circuit per se unstable to cause difficulty in satisfying the jitter specification (standard) in the SONET system.
On the other hand, since a complete integrator is employed in the integrator 13 in the circuit of FIG. 9, if DC offset voltage is present in the circuit, such offset voltage is integrated by the complete integrator to finally lead out an integrator output voltage maintained at an upper limit or a lower limit of the dynamic range of the circuit to make it impossible to obtain operation of the PLL circuit.